From memory (hopefully I’m remembering correctly):
Two of the DRAM chips provide the main memory (32K) and the shadow memory (20K) plus the extra workspace area (12K).
The remaining two DRAM chips provide all the sideways RAM (4 X 16K). For these, /CAS will only go active if the processor tries to access them. If both the links are set to enable the ROM sockets (the ROM sockets are each 32K) instead of the sideways RAM, /CAS will be held in the inactive state.
/RAS should be cycling for all four DRAM chips as that’s important for the DRAM refresh.
Mark
Two of the DRAM chips provide the main memory (32K) and the shadow memory (20K) plus the extra workspace area (12K).
The remaining two DRAM chips provide all the sideways RAM (4 X 16K). For these, /CAS will only go active if the processor tries to access them. If both the links are set to enable the ROM sockets (the ROM sockets are each 32K) instead of the sideways RAM, /CAS will be held in the inactive state.
/RAS should be cycling for all four DRAM chips as that’s important for the DRAM refresh.
Mark
Statistics: Posted by 1024MAK — Sat Jan 11, 2025 5:16 pm