Hi All, I'm hoping somebody can provide some help with memory instantiation using the GOWIN tools, specifically ROMsI've had a hack at beebfpga and I have got it doing something. No psram or anything yet. It's a bit messy I had to hack a few things to get it to allow vhdl 2008, otherwise my rom infer code didn't work.
Its on https://github.com/dominicbeesley/BeebF ... dev-tang9k
Time for bed but I won't be able to sleep!
I am trying to infer ROM's using the typical standard VHDL template you would use for Xilinx etc. i.e. a rom array but am having issues when I create more than 1 rom. It appears to use too much resource and often "sweeps" the ROM away for no reason. I see from the above post that problems were encountered and I noticed that the format of the "saa5050_rom_dual_port.vhd" file looks to be a combination of the instantiated format using the IP tools along with some manual changes. Can somebody please confirm how this was created. Do you have a tool to create them or was it a lot of manual work ?
Many thanks
Statistics: Posted by Budgie — Sat Mar 15, 2025 4:17 pm