Per the VL86C020 datasheet ("Cache Operation" section), the ARM core synchronizes to MCLK for all writes, and for reads that miss in the cache.So if doing something like video work, does the arm core just sit waiting? It is there some clever buffer interface between them?All derived timings should be derived from MCLK (since that's used for I/O), which isn't changing here (it'll be 12 MHz on an A5000, 8 MHz on an A3000 with an ARM3 upgrade); this is changing FCLK, which only affects the CPU and any FPA attached to it.
There are complicated rules (set out under the title "Instruction speeds") for when it synchronizes to MCLK, and for when it synchronizes to FCLK. The core takes at most FCLK cycle of delay to synchronize to FCLK. It takes at most 1 FCLK + 2 MCLK cycles of delay to synchronize to MCLK. Additionally, the CPU will fetch 16 sequential bytes (4 instructions) at a time to cache (running at MCLK) when it has a cache miss for an instruction fetch.
The key to the rules is that the core tries to stay synchronized to FCLK for as much time as possible, but holds at MCLK whenever it knows that it's immediately going to access RAM again (LDM/STM, instruction fetch). You can calculate the worst case time by assuming that it'll take the maximum possible time to change clocks, and the best case by assuming that it won't take any time to switch between MCLK and FCLK.
No clever buffering, just a slowdown whenever the CPU core accesses memory instead of cache. In practice, though, because ARM2 ran faster if you kept data in registers and used LDM/STM in preference to LDR/STR for anything involving more than 1 register, ARM3 gets a lot of boost from the cache - code was already written to run from registers wherever possible, and to use LDM/STM for bulk data moves,
Note that on ARM2, the reason for slowdown was different; ARM2 would use S cycles (faster) where permitted for instruction fetch if the previous instruction only operated on registers and immediates, and would also use S cycles where permitted for the second and subsequent data accesses in an LDM/STM. In all other cases (S cycles not permitted, branches, first data access in an LDM/STM, LDR/STR data access, first instruction fetch after an LDM/STM/LDR/STR/B), it'd use a slower N cycle.
Statistics: Posted by farnz — Fri Jun 20, 2025 12:18 pm