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32-bit acorn hardware • Re: Halfword access on RISC PC

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To answer an earlier question from paulb - I suspect there actually isn't a way to trap all LDRH and patch process it - you'd need to have some kind of selective abort system to fault 'unfaulty' instructions, because at the processor level, it'll believe it's all ok.
Yes, I was assuming that it wasn't supported on the StrongARM, but then I discovered that it was. So it isn't an unrecognised instruction and therefore won't cause an exception. And Sarah has concisely described the problem: that the accesses aren't presented appropriately and produce bad results, meaning that the strategy of avoiding LDRH presumably employed by Acorn won't work in a world where all the compilers want to generate it.

Well now, does anyone want to make some "trivial" changes to GCC?

Statistics: Posted by paulb — Mon Feb 03, 2025 8:07 pm



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