Given the Acorn large memory 6502 2nd processor gives a civilised (to programmers) linear 24bit data address space via zp indirect, as described in this thread, I wondered if something similar could be done for subroutine calls, allowing a simple long call to 24bit linear address (eg an indirect BSR thru a 24bitbaddress in same zp and page 3 combo, although that is codespace inefficient OR a 6812-like* CALL/RTC pair but unlike it, our address operand is a simple 24bit linear address) but they both seem to need hardware to create new opcodes....
whereupon I discovered already done (recently-ish) by a statdot member viewtopic.php?p=33659 who created the https://laughtonelectronics.com/Arcana/ ... mmary.html
If Acorn had created something similar with a Ula for the logic, that could have made such a large memory 6502+ a useful upgrade in the wilderness years till the Arm?
whereupon I discovered already done (recently-ish) by a statdot member viewtopic.php?p=33659 who created the https://laughtonelectronics.com/Arcana/ ... mmary.html
If Acorn had created something similar with a Ula for the logic, that could have made such a large memory 6502+ a useful upgrade in the wilderness years till the Arm?
Statistics: Posted by B3_B3_B3 — Mon Jan 27, 2025 8:07 pm