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8-bit acorn hardware • Re: SDC timing constraints question

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“ What we're constraining is all the paths between registers inside the t65 cpu not the clock enable. The clock enable should be in the fast clock domain and last for a single cycle of the fast clock. You probably won't need any special treatment for the timing of that.”

Thanks Dominic the above information was key to me understanding what to constrain. My problem now is finding if I can use wild cards as the number of entries is loads to include every register within the CPU

Statistics: Posted by Budgie — Tue Jan 21, 2025 7:14 pm



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